Call for submissions
Download the Call for Submissions
Topic Areas – You are invited to participate and submit your contributions to the 3D & Chiplet TEST Workshop. The workshop’s areas of interest include (but are not limited to) the following topics:
- Defects due to Wafer Thinning
- DfT Architectures for 3D systems
- D2D PHY monitoring, test & repair
- EDA DfT Flow for 3D packages
- Lane Fault Models & Failure Analysis
- Fault-Tolerant Design for multi-die
- Handling and Testing Singulated stacks
- HBM base-die & stack test & repair
- Interposer Testing & Debugging
- Known-Good Die / Known-Good Stack
- Monitor interconnect signal integrity
- Pre-, Mid-, and Post-Bond Testing
- RAS for chiplet-based systems
- Stacking Yield, Redundancy & Repair
- Standards for 3D Test & Repair, P3405 1838
- Standards for test description 3dBlox
- Test Cost Modelling for 3D Packages
- Test Flow Optimization for 3D Packages
- Tester Architecture incl. ATE and BIST
- TSV-based lane test & repair
- UCie-based Multi-Die Test & Debug
- Wafer Probing and Probe Marks of 3D-SICs
Submission Instructions: Submissions must be sent as PDF files. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results.
Publications: 3D & Chiplet TEST focuses on early information sharing and free discussions; therefore, the workshop will not publish formal proceedings. Instead, the workshop will make available to all its registered participants an electronic workshop digest, which includes all material that authors/presenters are willing to contribute in PDF format: abstract, paper, slides, posters, background material, etc. This will allow authors to be free in their choice to submit their workshop paper later to a formal (IEEE or otherwise) journal, leveraging the audience feedback and discussions on the paper presentation at the 3D & Chiplet TEST Workshop.
Key Dates & Deadlines:
Submission deadline: June 27 July 13, 2025
Notification of acceptance: July 18, 2025