The 3D & Chiplet TEST Workshop focuses exclusively on test and repair of chiplet-based stacked ICs, including 2.5D and 3D-Stacks based on hybrid bonding, through-silicon vias (TSVs), micro-bumps, and/or interposers.

While these multi-die packages offer many attractive advantages, such as heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many challenges with respect to testing, monitoring and repairing such chiplet-based systems.

The 3D & Chiplet TEST Workshop offers an ideal forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.

The 9^th edition of 3D & Chiplet TEST takes place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the IEEE Philadelphia Section in concurrence with the Test Technology Technical Council (TTTC) of IEEE Computer Society.

Submission: Submissions must be sent as PDF files. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results.

Publications: 3D & Chiplet TEST focuses on early information sharing and free discussions; therefore, the workshop will not publish formal proceedings. Instead, the workshop will make available to all its registered participants an electronic workshop digest, which includes all material that authors/presenters are willing to contribute in PDF format: abstract, paper, slides, posters, background material, etc. This will allow authors to be free in their choice to submit their workshop paper later to a formal (IEEE or otherwise) journal, leveraging the audience feedback and discussions on the paper presentation at the 3D & Chiplet TEST Workshop.

Download the Call for Contribution!